Personal computer systems have been designed which are adapted to use Single Inline Memory Modules (SIMMs) as on-board memory. The SIMMs utilize random access memory (RAM) which can be either dynamic random access memory (DRAMs) or static random access memory (SRAMs). The computer system utilizes a memory controller in the form of an integrated circuit (IC) chip which controls the various signals which are sent from the central processing unit (CPU) to the memory to either write data to or read data from the memory. The memory controller is designed to accommodate certain configurations of DRAM chips and SIMMs. For example, a common SIMM has been a 72-pin SIMM which utilizes 16 1M.times.4 DRAM chips to provide 8 megabytes of memory. This configuration allocates a certain number of pins for addressing memory locations and provides two row activation signals (RAS) for activating the DRAMs on either read or write cycles. The DRAMs are functionally arranged in two sets of 8 chips each, with each set having ten row addresses and ten column addresses. Such an address configuration is known as a 10.times.10. Thus, the need arises for two RAS's, one RAS for one of the sets of 8 chips and one for the other set of 8 chips. Hence, this scheme is known as 10.times.10 addressing with two sets of addressable chips. To address one set of DRAM chips, one of the RAS signals is driven active, and to address the other set of DRAM chips the other RAS signal is driven active.
As chip technology progresses and larger size chips become cheaper, it becomes economical to replace several chips with a single chip. One particular configuration of chips which has become readily available at attractive prices is a 2M.times.8 chip, which contains four times the amount of data as a 1M.times.4. Thus, 4 2M.times.8 chips can store the same amount of data as 16 1M.times.4 chips. Thus, these chips are desirable to be utilized on a SIMM for cost reasons. However, it is desirable in providing or utilizing these more cost-effective chips that they be utilized in systems having pre-existing memory controllers which have been designed for the 1M.times.4 chips. This causes a problem. The 2M.times.8 SIMMs require 11 row addresses rather than the 10 required by the 1M.times.4 chips, and thus there is not the available row address without the addition of another pin and significant redesign--and even then the design becomes difficult because all 72 pins have normally been utilized. However, only one RAS signal is needed to activate the read or write functions of the four chips. Thus, one technique to overcome the 11 row limitation is by utilizing the signal on one of the RAS lines to function as an address bit on the 11th row address space. While this does work, it has certain disadvantages. One of the disadvantages is that utilizing one of the RAS's directly on the 11th address bit will not accommodate a refresh function when refresh is done by both RAS's going low, known as ROR (RAS Only Refresh), rather than the refresh function being performed by a CAS before RAS signal configuration known as CBR (CAS Before RAS). This is because the 11th address bit will always be active when both RAS's go active, thus refreshing only one-half of the chip, i.e., the address portion of the chip utilizing the active bit in the 11th address space which is the most significant bit. Another problem is that since only a single RAS activation is necessary for the 2M.times.8 chips, logic such as an AND gate is necessary to perform a row activation function when either RAS input goes low. This additional logic can lead to timing problems, especially with respect to the timing in which activation of the 11th row address takes place, vis-a-vis, the activation of the RAS signal on the chip following the logic circuitry to combine the two RAS signals as a single master RAS signal.
It is therefore an object of the present invention to provide a computer system and SIMM configuration and method of operation which allows DRAMs having a greater number of row address than are supplied by a memory controller to be used by a system using such a memory controller.